The present invention relates to an address specifying mechanism in a computer, and in particular, to an address space switching or change-over apparatus suitable for extending an address space.
In scientific and technological computations and data base processing, the amount of data to be processed has recently been increasing. In order to efficiently process a great amount of data, it is desirable in general that a large address space is available for a computer. However, if the address space is extended for any processing, it is necessary to change specifications of almost all the instructions and to prepare a large number of new instructions, and as a result, the size of the hardware is increased and a great amount of the existing software is required to be modified.
In order to solve the problems above, there has been proposed a system in which only an address space for data (only an operand address space) is extended and an address space for instructions, namely, an instruction address space is kept remained as in the conventional system. An example of such a system has been described in the Japanese Patent Examined Publication No. JP-B-60-53895. The instruction address rarely becomes insufficient for a program to process a great amount of data. In many cases, the processing efficiency can be remarkably improved by extending only the operand address space. In consequence, it can be regarded as a practical approach to extend only the operand address.
However, in the conventional computer of the type described above, the address extension is restricted by the address space defined by a length (for example, a work length, and in general, the number of bits of a group of registers) of an information unit which can be processed at a time by the computer in association with the structure thereof and therefore it is impossible to exceed the limit in the operand address extension.